1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including electrically rewritable memory cells and a method of data write/data erase therein.
2. Description of the Related Art
In recent years, along with a rising level of integration in semiconductor devices, circuit patterns of transistors and the like which configure the semiconductor devices are being increasingly miniaturized. Required in this miniaturization of the patterns is not simply a thinning of line width but also an improvement in dimensional accuracy and positional accuracy of the patterns. This trend applies also to semiconductor memory devices.
Conventionally known and marketed semiconductor memory devices such as DRAM, SRAM, and flash memory each use a MOSFET as a memory cell. Consequently, there is required, accompanying the miniaturization of patterns, an improvement in dimensional accuracy at a degree exceeding a degree of the miniaturization. As a result, a large burden is placed also on the lithography technology for forming these patterns which is a factor contributing to a rise in product cost.
Accordingly, resistive memory is attracting attention as a candidate to succeed these kinds of semiconductor memory devices that utilize a MOSFET as a memory cell (refer, for example, to Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-522045). The resistive memory herein includes a resistive RAM (ReRAM), and a phase Change RAM (PCRAM). The ReRAM, in a narrow sense, uses a transition metal oxide as a recording layer to store its resistance states in a non-volatile manner. The PCRAM uses chalcogenide or the like as a recording layer to utilize the resistance information of crystalline states (conductors) and amorphous states (insulators).
Two kinds of variable resistors in the aforementioned resistive memory are known. In one kind, known as a bipolar type, a high-resistance state and a low-resistance state are set by switching a polarity of an applied voltage (refer, for example, to OYO BUTURI (Applied Physics), Vol. 75, No. 09, p. 1109). In the other kind, known as a unipolar type, setting of the high-resistance state and the low-resistance state are made possible by controlling a voltage value and a voltage application time, without switching the polarity of the applied voltage.
In the case of bipolar type resistive memory, a memory cell array is configured by overlapping a variable resistor and a rectifier at crossing-points of bit lines and word lines, the rectifier being such as a MIM diode having non-linear current-voltage characteristics for both positive and negative polarities. Furthermore, arranging such memory cell arrays three-dimensionally in stacks enables a large capacity to be realized without transistors and causing an increase in cell array area.
Write of data to a memory cell is performed by applying to the variable resistor a short-lasting voltage pulse with a certain polarity. The variable resistor thereby changes from the high-resistance state to the low-resistance state. Hereinafter, this operation to change the variable resistor from the high-resistance state to the low-resistance state is called a setting operation.
In contrast, erase of data in a memory cell is performed by applying to the variable resistor in the low-resistance state subsequent to the setting operation a short-lasting voltage pulse with a polarity opposite to that of the short-lasting voltage pulse applied during the setting operation. The variable resistor thereby changes from the low-resistance state to the high-resistance state. Hereinafter, this operation to change the variable resistor from the low-resistance state to the high-resistance state is called a resetting operation. For example, in the case of binary data storage where the memory cell has the high-resistance state as a stable state (reset state), data write is performed by the setting operation which changes the reset state to the low-resistance state.
As described above, when driving a bipolar type memory cell, the memory cell must be applied with voltage pulses having a polarity that differs for setting and resetting. Consequently, in the case of bipolar type resistive memory, there is a need to configure voltage pulse generating circuits for generating, for example, a voltage pulse of a positive polarity on both an upper electrode side and lower electrode side of the memory cell. Alternatively, it becomes necessary to configure a voltage pulse generating circuit capable of generating a voltage pulse of both a positive and negative polarity on either of the upper or lower electrode sides. These both imply a large increase in area of peripheral circuits of the memory, and are thus a barrier to improving a level of integration in the memory.